Gujarat Extends Its Semiconductor Bet From Fabs to Chip Design

The Gujarat government's Department of Science and Technology, operating through the Gujarat State Electronics Mission (GSEM), has proposed establishing a ChipIN Extension Centre and a Centre of Excellence (CoE) for Very Large Scale Integration (VLSI) Design. The centre will be located at the Gujarat Technological University (GTU) campus and developed in collaboration with the Centre for Development of Advanced Computing (C-DAC). A two-day orientation programme began on 7 August 2026, with more than 30 academic institutions from across Gujarat participating. The initiative aims to give engineering colleges cloud-based access to advanced Electronic Design Automation (EDA) tools - including those from Cadence, Synopsys and Siemens - in a phased manner, alongside expert training on the full semiconductor design workflow.

The strategic significance lies in Gujarat's deliberate move to ascend the semiconductor value chain beyond manufacturing. The state already hosts significant fabrication and assembly investments, including Tata Electronics' planned fab in Dholera and Micron's assembly-and-testing facility in Sanand. By adding chip-design capability, Gujarat is positioning itself to capture higher-value activities in the semiconductor ecosystem, where design IP and architecture development command substantially greater margins than backend assembly and testing.

The dependency frame is instructive. Chip design in India has historically been concentrated in Karnataka (Bengaluru) and Hyderabad, with limited capability development in Gujarat despite its manufacturing base. This initiative addresses a structural gap by providing students and researchers a route to fabrication through the Multi-Project Wafer (MPW) programme, enabling academic chip designs to be converted into physical silicon for testing. This hands-on pathway from design to fabrication is rare in Indian higher education and could stimulate a new generation of semiconductor startups in the state.

The test to watch is whether the phased rollout of EDA-tool access reaches a critical mass of engineering colleges, and whether the MPW fabrication pipeline produces commercially viable chip designs from academic institutions. Success will depend on sustained industry engagement, the availability of experienced VLSI professionals as trainers, and the alignment of curricula with industry requirements. If it works, the model could be replicated across other states pursuing semiconductor-ecosystem development under the Semicon 2.0 framework.